1. Technical Field
The present invention relates to a non-volatile memory device, and more particularly to a method of reading data from a non-volatile memory device and method of inputting and outputting data using the method of reading data.
2. Description of the Related Art
Semiconductor memory devices are microelectronic devices that are widely used in the design of digital logic circuits such as microprocessor-based applications and computers for products ranging from satellites to consumer electronics. Advances in memory devices have raised the performance of digital logic systems.
Semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices. The nonvolatile memory devices can retain data even when power supply is disconnected. Data stored in the nonvolatile memory devices may be permanent (read only) or reprogrammable (write, read). The nonvolatile memory devices are now widely used to store executable programs or microcodes in various applications such as computers, avionics, communications, and consumer electronic technologies.
An example of the nonvolatile memory device is a flash memory device. A flash memory device may be classified into a single-level cell (SLC) type and a multi-level cell (MLC) type according to the number of bits stored in one memory cell. The single-level cell (SLC) stores a logic level of one bit in one memory cell, and each cell is characterized by one specific threshold voltage, or one Vt level.
FIG. 6A is a circuit diagram illustrating a conventional multi-level cell (MLC) of a non-volatile memory device. Each multi-level cell (MLC) stores logic levels of two or more bits in one memory cell. In MLC technology, the threshold voltage of each cell has been divided into greater than two levels. FIG. 6B is a threshold voltage distribution diagram illustrating an example of threshold voltages of a multi-level cells and the logic states corresponding to the threshold voltages. A multilevel cell, for storing n bits per cell, is programmed on m=2n voltage levels. In FIG. 6B, the multi-level cell (MLC) stores two (n=2) bits in each one memory cell, and thus has four (m=22) threshold voltages. Architecturally, Flash Memory is classified into two types, namely NOR Flash Memory and NAND Flash Memory. A NOR-based Multi-Level Cell architecture provides direct memory-cell access. NAND-based flash has no provision for a random-access. Memory cells are organized serially in NAND-based flash architecture owing to which the data is read block-wise basis. The typical block sizes may comprise of multiple bits in thousands.
The size of a memory device may be reduced when the memory device is operated as the multi-level cell (MLC) type since the multi-level cell may store more bits in one memory cell than the single-level cell. However, as the number of bits stored in the multi-level cell increases, a plurality of read voltages must be applied to the multi-level cells in order to read data from the multi-level cell, and thus an initial read time including the sensing time and the output time increases, thereby degrading performance of the memory device.
In a synchronized reading operation in a non-volatile memory device such as a flash memory, the sensing time for sensing data stored in a memory cell and the output time for outputting the sensed data delays the output of valid data. When the sensing time and the output time become longer, performance of the non-volatile memory device operates is degraded. Therefore, it is desirable to reduce the sensing time and the output time for enhancing the operation speed (frequency) of the non-volatile memory device.